1. Field of the Invention
The present invention relates to apparatuses for receiving television and radio broadcasting, especially digital broadcasting.
2. Description of the Background Art
Shown in FIG. 21 is the structure of a conventional digital broadcast receiving apparatus. A digital broadcast receiving apparatus Rc includes an antenna 1, a tuner 2, an A/D converter 3, a demodulator 7, and an automatic gain controller AGC. The automatic gain controller AGC includes an automatic gain control signal generator (hereinafter referred to as AGC signal generator) SG, and a level detector LD. A digital broadcast wave RF transmitted from a broadcasting station is propagated through the air and received by the antenna 1. The received digital broadcast wave Srf is frequency-converted by the tuner 2 into a modulated analog signal SMA. This modulated analog signal SMA is converted by the A/D converter 3 into a modulated digital signal SMD, and then outputted to the automatic gain controller AGC and the demodulator 7.
In the automatic gain controller AGC, the level detector LD detects the level of the received modulated digital signal SMD, and determines whether the detected signal level is higher than a predetermined level (reference value) or not for generating a level signal SL. The AGC signal generator SG generates, based on the level signal SL supplied by the level detector LD, a control signal SAG for adjusting the gain of the tuner 2, and outputs the control signal SAG to the tuner 2. In other words, if the signal level is larger than the predetermined level (reference value), the level detector LD causes the AGC signal generator SG to output the control signal SAG for decreasing the gain of the tuner 2. On the other hand, if the signal level is equal to or lower than the predetermined level (reference value), the level detector LD causes the AGC signal generator SG to output the control signal SAG for increasing the gain of the tuner 2.
After the gain of the tuner 2 is controlled, the modulated analog signal SMA is converted by the A/D converter 3 into the modulated digital signal SMD. Then, from this modulated digital signal SMD, a demodulated digital signal SDD is generated by the demodulator 7 for output to the following error correction processing.
Shown in FIG. 22 is the structure of the level detector LD in detail. The level detector LD includes a subtractor 12, an adder 13, a delay unit 14, and a bit shifter 15 (represented as “2−n” in FIG. 22). Note that n represents the number of shift bits. The adder 13 and the delay unit 14 form an integrator 100. For example, if an average value is obtained from 4096=212 values of data, the bit shifter 15 is set as n=12. An averaged signal Y/2n received from the bit shifter 15 is subtracted by the subtractor 12 from the modulated digital signal SMD supplied by the A/D converter 3, and the result is outputted to the integrator 100.
Shown in FIG. 23 is the structure of the AGC signal generator SG in detail. The AGC signal generator SG includes a reference value provider 16, a subtractor 24, a multiplier 17, a constant provider 18, an integrator 21, a level converter LC, a PWM (Pulse Width Modulator) 22, and a low-pass filter 23. The integrator 21 includes an adder 19 and a delay unit 20. The level converter LC includes a multiplier 33, an inverse coefficient provider 34, a compensation coefficient provider 46, and an adder 47.
The subtractor 24 finds an error between the level signal SL supplied by the level detector LD and a predetermined reference value R supplied by the reference value provider 16 to generate an error signal SE. Note that, for the purpose of simplifying the description, signals and parameters may hereinafter be simply represented by reference characters as appropriate. The multiplier 17 multiplies the error signal SE received from the subtractor 24 by a constant G received from the constant provider 18 to generate G·SE for output to the integrator 21.
In the integrator 21, the delay unit 20 first delays G·SE outputted from the multiplier 17 by a control cycle t, and then the adder 19 adds the delayed signal to a current output from the multiplier 17 for integration of G·SE. The integration result is outputted as an integrated signal Z from the delay unit 20 to the adder 19 and the level converter LC. Note herein that one control cycle is a sequence of control processing successively carried out in the digital broadcast receiving apparatus Rc and a digital broadcast receiving apparatus RPa according to the present invention, and their components. Also note that one control cycle period is a time period required for execution of one control cycle, that is, a period from start of one control cycle until before start of the next control cycle.
In the level converter LC, the multiplier 33 multiplies the integrated signal Z outputted from the integrator 21 by “−1” outputted from the inverse coefficient provider 34 to invert the polarity of the integrated signal Z, and generates −Z. The adder 47 adds a compensation coefficient OB provided by the compensation coefficient provider 46 to −Z provided by the multiplier 33, and generates −Z+OB. The PWM 22 modulates the pulse width of −Z+OB received from the adder 47 to generate a square-wave signal Sr. The low-pass filter 23 extracts low-frequency components from the square-wave signal Sr supplied by the PWM 22 to generate the control signal SAG having a predetermined control voltage. Consequently, the tuner 2, the level detector LD, and the AGC signal generator SG form a loop.
The level converter LC is briefly described below. The level converter LC is provided to normalize the value of the integrated signal Z outputted from the integrator 21 before processed by the PWM 22 for correct gain control if the value of integrated signal Z is larger than the reference value. Therefore, the inverse coefficient provider 34 provides the inverse coefficient, that is, a predetermined negative value, to the multiplier 33 for inverting the polarity of the integrated signal Z. The compensation coefficient provider 46 provides, for the sake of convenience of the processing in the PWM 22, the compensation coefficient OB having a predetermined value for compensating the inverted integrated signal Z (−Z) so that it takes a positive value or 0 at the output from the level converter LC.
The value of the compensation coefficient OB is determined based on the inverse coefficient provided by the inverse coefficient provider 34 and the number of output bits of the integrator 21. Now, consider the case where the inverse coefficient is −1, and the number of output bits of the integrator 21 is 11. In this case, the integrated signal Z takes a value in the range of −1024 to +1023. If the compensation coefficient OB is set to 11 bits (1024), which is the number of output bits of the integrator 21, the value of −Z+OB outputted from the adder 47 falls within the range of 0 to +2047. −Z+OB takes a value of +1024 (OB) if the output from the integrator 21 is 0, while taking a value in the range of +1025 to +2047 if negative. As such, correct gain control can be achieved according to fluctuations of the digital broadcast wave Srf.
FIGS. 22 and 23 schematically illustrate processes on various signals generated in the level detector LD and the AGC signal generator SG in an arbitrary control cycle t. Throughout this specification, the control cycle is represented as t. That is, a control cycle previous to the control cycle t is represented as t with a natural number added thereto, and the one next thereto as t with a natural number subtracted therefrom. As such, the control cycle t is also a parameter indicating a relative time. Furthermore, for the sake of convenience, the control cycle t may be simply referred to as “t”, and also each signal and parameter may be referred to as its reference character.
As shown in FIG. 22, the subtractor 12 of the level detector LD subtracts the averaged signal Y(t+1)/2n supplied by the bit shifter 15 from SMD(t) supplied by the A/D converter 3 to generate SMD(t)−Y(t+1)/2n.
The adder 13 of the integrator 100 adds SMD(t)−Y(t+1)/2n supplied by the subtractor 12 to the integrated signal Y(t+1) supplied by the delay unit 14 to generate SMD(t)−Y(t+1)/2n+Y(t+1)=SMD(t)+Y(t+1)(1−2−n).
The delay unit 14 delays SMD(t)+Y(t+1)(1−2−n) outputted from the adder 13 by one control cycle t to generate an integrated signal Y(t+1).
The bit shifter 15 shifts the integrated signal Y(t+1) by the predetermined number of shift bits n to generate an averaged signal Y(t+1)/2n. This averaged signal Y(t+1)/2n is equivalent to the average of 2n data values of the modulated digital signal SMD supplied to the level detector LD. In this sense, the number of shift bits n defines the number of data values required for finding the average value by the bit shifter 15. In other words, 2n is the number of data values required for finding the average value of the modulated digital signal SMD supplied to the level detector LD, and the number of shift bits n is an averaging coefficient. Hereinafter, 2n is referred to as the number of data values for averaging.
Next, as shown in FIG. 23, the subtractor 24 of the AGC signal generator SG subtracts the reference value R provided by the reference value provider 16 from the level signal SL supplied by the level detector LD to generate the error signal SE(t).
The multiplier 17 multiplies SE(t) supplied by the subtractor 24 by the constant G provided by the constant provider 18 to generate G·SE(t).
The adder 19 of the integrator 21 adds G·SE(t) supplied by the multiplier 17 to the integrated signal Z(t+1) outputted from the delay unit 20 to generate G·SE(t)+Z(t+1).
The delay unit 20 delays G·SE(t)+Z(t+1) supplied by the adder 19 by one control cycle t to generate the integrated signal Z(t+1).
The inverse coefficient provider 34 of the level converter LC multiplies the integrated signal Z(t+1) received from the delay unit 20 by the inverse coefficient “−1” provided by the inverse coefficient provider 34 to generate −Z(t+1).
The adder 47 adds −Z(t+1) supplied by the multiplier 33 to the compensation coefficient OB provided by the compensation coefficient provider 46 to generate −Z(t+1)+OB.
The PWM 22 converts the pulse width of −Z(t+1)+OB supplied by the level converter LC to generate a square-wave signal Sr. The low-pass filter 23 extracts low-frequency components from the square-wave signal Sr supplied by the PWM 22 to generate the gain control signal SAG at a desired stable level.
In the above structured digital broadcast receiving apparatus Rc, if the signal of the digital broadcast wave Srf becomes maximum and accordingly the level signal SL becomes maximum, −Z+OB becomes 0 and the square-wave signal Sr becomes constant at 0, as shown in FIG. 24. The control signal SAG therefore becomes minimum. If the digital broadcast wave Srf becomes intermediate and accordingly the level signal SL becomes intermediate, −Z+OB becomes 1024 and the square-wave signal Sr alternately indicates 0 and 1, as shown in FIG. 25. The control signal SAG therefore becomes intermediate. If the digital broadcast wave Srf becomes minimum and accordingly the level signal SL becomes minimum, −Z+OB becomes +2047 and the square-wave signal Sr becomes constant at 1, as shown in FIG. 26. The control signal SAG therefore becomes maximum.
Exemplarily shown in FIG. 27 is a relation between the digital broadcast wave Srf and the modulated analog signal SMA in the above structured digital broadcast receiving apparatus Rc. In FIG. 27, SW1 in the upper part represents a signal waveform of the digital broadcast wave Srf in a relatively short period of time. SW2 in the middle part represents an envelope waveform of the digital broadcast waveform Srf in a period considerably longer than that shown by SW1. In this example, the digital broadcast wave Srf fluctuates in amplitude within 6 dB and in frequency within 100 Hz. SW3 in the lower part represents a signal waveform of the modulated analog signal SMA outputted from the tuner 2 after fluctuations are eliminated from the digital broadcast wave Srf (SW2). With a smaller number of data values used for level detection by the level detector LD (for example, 127,27) and a larger value of the constant G used for multiplication by the multiplier 17 of the AGC signal generator SG (for example, 128), the modulated analog signal SMA outputted from the tuner 2 can be made not to fluctuate in frequency. That is, the digital broadcast receiving apparatus Rc can follow the frequency fluctuations of the received digital broadcast wave Srf.
In the above digital broadcast receiving apparatus Rc, it has been confirmed through experiments that a maximum followable fluctuation frequency of the digital broadcast wave Srf whose amplitude fluctuates within 6 dB is approximately 100 Hz. Specifically, with the smallest possible number of data values (the number of shift bits n) used for level detection in the level detector LD and the largest possible constant G, the above apparatus can generate the modulated analog signal SMA without frequency fluctuations from the digital broadcast wave Srf whose amplitude fluctuates within 6 dB and whose frequency fluctuates up to 100 Hz. Such frequency fluctuations of 100 Hz are caused by an object moving at 180 km per hour toward the digital broadcast wave Srf emitted from a broadcast station or a relay station and propagated through the air to reach the digital broadcast receiving apparatus Rc.
However, the digital broadcast wave Srf whose frequency fluctuates within the maximum followable fluctuation frequency (100 Hz) may often fluctuate thereover due to swaying leaves, collision with a moving object such as a vehicle, or reflection from a fast-moving object such as an airplane. In such case, the digital broadcast receiving apparatus Rc cannot follow the frequency fluctuations of the digital broadcast wave Srf, and therefore cannot reproduce the demodulated digital signal SDD with high quality.
Moreover, the ratio of control voltage to gain in the tuner 2 is varied depending on the level of the digital broadcast wave Srf supplied thereto. Therefore, the capability of following frequency fluctuations is also varied depending thereon, and so is the quality of the demodulated digital signal SDD accordingly.
As stated above, in conventional analog broadcast typified by NTSC, a received broadcast wave reflected upon a fast-moving object, such as an airplane, causes deterioration in quality of a demodulated signal. Such deterioration further causes image disturbance, but does not interrupt images. In digital broadcast, however, the demodulated digital signal SDD deteriorated in quality causes a complete interrupt of a video stream.